1. Field of the Invention
The present invention relates to an algorithm analog-to-digital converter (ADC) and, more particularly, to an algorithm ADC in which a linearity limitation resulting from capacitor mismatch and power consumption are minimized. The present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication)/IITA (Institute for Information Technology Advancement) [2006-S-006-01, Components/Module technology for Ubiquitous Terminals] in Korea.
2. Discussion of Related Art
In an image system, in order to process an image signal, a fine analog signal should be converted into a digital signal which is robust to noise, and conversion of from an analog signal to a digital signal is performed by an analog-to-digital converter (ADC).
A high resolution ADC which can discriminate small signals is necessary since image information output from a sensor can be very fine. In addition to the image system, communication systems and image processing application systems such as a mobile communication system, an asynchronous digital subscriber loop (ADSL) system, an IMT-2000 system, a digital camcorder system, and a high definition television (HDTV) also need a high performance ADC which has a high resolution of a 12-bit level to a 14-bit level and a high sampling speed of tens of megahertz level.
Among various conventional ADCs, an algorithm ADC is widely used to optimize power consumption and the chip area size, and a structure of such an algorithm ADC is shown in FIG. 1.
FIG. 1 is a circuit diagram illustrating a conventional algorithm ADC.
As shown in FIG. 1, the conventional algorithm ADC comprises a sample-and-hold amplifier (SHA) 1 for sampling and holding an input analog voltage, a flash ADC 3 for converting the input analog signal into a digital signal and outputting the digital signal, a multiplying digital-to-analog converter (MDAC) 5 for converting a difference between the digital signal output from the flash ADC 3 and a signal output from the SHA 1 into an analog signal and outputting the analog signal, and a digital correction circuit 7 for correcting an error of the digital signal output from the flash ADC 3. The algorithm ADC of FIG. 1 has an overall n-bit resolution.
In the conventional algorithm ADC, the MDAC 5 comprises one amplifier and a plurality of capacitors. A mismatch between the capacitors affects differential nonlinearity of the whole ADC, so that the given resolution is limited.
In order to resolve the above problem, U.S. Pat. No. 6,097,326 discloses an algorithm ADC with reduced differential nonlinearity in which capacitor connections are different from each other and output analog values are added, so that an effect of a mismatch between the capacitors is minimized.
The algorithm ADC with reduced differential nonlinearity is configured such that two analog values output through different capacitor connections are added to thereby remove the effect of a capacitor mismatch. A maximum analog value which can be processed in an analog area is restricted, and thus the size of each signal should be reduced to half before being processed in order to add the two output values. In a case where the size of each signal is reduced to half, a signal to noise ratio (SNR) to each analog signal (thermal noise excluding an SNR caused from a capacitor mismatch and SNR generated in an amplifier) is relatively increased.
The technique for removing a mismatch in the analog area, which is applied to the algorithm ADC with reduced differential nonlinearity, has the following problems. First, the SNR is 6 dB lower compared to a case where the mismatch removing technique is not applied, and if a first analog output value and a second analog output value are added the SNR is increased by 3 dB in total, because the SNR does not have a correlation. Thus, the use of the mismatch removing technique leads to SNR improvement by 3 dB, but results in a total SNR loss by 3 dB, which limits linearity of the ADC, unlike nonuse of the mismatch removing technique.
Also, since a signal conversion operating cycle is constant, due to the conventional algorithm ADC's use of a constant clock cycle, more than the necessary power may be consumed during even a cycle for outputting a low bit.
In more detail, in the algorithm ADC structure, a signal on an output terminal of the MDAC is required to have a
  1      2          n      -      i      accuracy level at an i-th clock phase, and since an operating speed of the amplifier required in the i-th MDAC is in proportion to ln(2n−i), the MDAC is designed to have an
      n    -    i        n    -          (              i        +        1            )      faster operating speed at an i-th clock phase than at (i+1)-th clock phase.
For example, in a 12-bit ADC, since the MDAC should output a signal at a first clock phase with the accuracy of 11 bits, and at a second clock phase with the accuracy of 10 bits, an operation of the MDAC at the first clock phase has to be 11/10 faster than an operation of the MDAC at the second clock phase. On the other hand, since the MDAC has the accuracy of 2 bits at the last clock phase (11-th clock phase), it can have a 2/11 lower operating speed than the first clock phase.
However, since the MDAC uses the same clock frequency at each phase, there is a problem in the conventional algorithm ADC in that more than the necessary power may be consumed at a clock phase for outputting a low bit.
In order to resolve the above problem, provided is a technique for minimizing power consumption at each phase in which a phase delay circuit is used to generate an appropriate delay signal, and cycles of respective clock phases which are different from each other are sequentially reduced by using the appropriate delay signal.
However, since the above described technique uses the delay signal, the cycle of each clock phase may be inaccurately controlled, whereby it can be difficult to achieve optimization of power consumption.